On Mon, 18 Mar 2013, Chris Wilson wrote:
> > +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> > void
> > intel_i2c_reset(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
> > - I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
> > + if (HAS_GMBUS_IRQ(dev))
> > + I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
>
> There should not be any harm in always clearing GMBUS4, it exists on all
> platforms.
>
> > }
> >
> > static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
> > @@ -203,7 +205,6 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
> > algo->data = bus;
> > }
> >
> > -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4)
> > static int
> > gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
> > u32 gmbus2_status,
> > @@ -214,6 +215,13 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
> > u32 gmbus2 = 0;
> > DEFINE_WAIT(wait);
> >
> > + if (!HAS_GMBUS_IRQ(dev_priv->dev)) {
> > + int ret;
> > + ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
> > + (GMBUS_SATOER | gmbus2_status),
> > + 50);
>
> This should couple up to the normal return code that chooses the
> appropriate return value based on gmbus2.
>
> How about just using:
> if (!HAS_GMBUS_IRQ(dev_priv->dev)) gmbus4_irq_en = 0;
> and the existing wait loop?
I explicitly wanted to avoid touching GMBUS4 register, as the real cause
of the failure is not clear.
But, as Yinghai Lu points out, the problem is most likely caused by
interrupt disabling not working properly (see his very good point
regarding DisINTx+ and INTx+ discrepancy), so zeroing the register out
should work .... and it indeed does in my case, hence the (tested) patch
below.
I think it's a 3.9-rc material, and I am all open to debug this further
for 3.10 so that the race is closed and gmbus irqs can be used on Gen4
platform properly.
From: Jiri Kosina <jkosina@xxxxxxx>
Subject: [PATCH] drm/i915: stop using GMBUS IRQs on Gen4 chips
Commit 28c70f162 ("drm/i915: use the gmbus irq for waits") switched to
using GMBUS irqs instead of GPIO bit-banging for chipset generations 4
and above.
It turns out though that on many systems this leads to spurious interrupts
being generated, long after the register write to disable the IRQs has been
issued.
Flushing of the register writes by POSTING_READ() directly after the register
write doesn't work either.
Disable using of GMBUS IRQs on Gen4 systems before the root cause is found and
revert back to old behavior.
Signed-off-by: Jiri Kosina <jkosina@xxxxxxx>
---
drivers/gpu/drm/i915/intel_i2c.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index acf8aec..9934724 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -203,7 +203,7 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
algo->data = bus;
}
-#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4)
+#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
static int
gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
u32 gmbus2_status,
@@ -214,6 +214,8 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
u32 gmbus2 = 0;
DEFINE_WAIT(wait);
+ if (!HAS_GMBUS_IRQ(dev_priv->dev))
+ gmbus4_irq_en = 0;
/* Important: The hw handles only the first bit, so set only one! Since
* we also need to check for NAKs besides the hw ready/idle signal, we
* need to wake up periodically and check that ourselves. */
--
Jiri Kosina
SUSE Labs
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