On Tue, Mar 12, 2013 at 3:22 AM, Xiangliang Yu <yuxiangl@xxxxxxxxxxx> wrote: > Hi, Myron >> > Now, the situation is like this: >> > I captured the PCIE trace with analyzer and found that 1st BE is 0x1111 >> > when >> > accessing IO port space. But 9125 spec has some limitation, and the BE >> > must >> > be >> > 0x0100, to access the 2nd byte only. So, the chip will go to bad. >> >> Great, this is new, interesting, data. Is the 9125 spec publicly >> accessible and/or could you elaborate on the "some limitation" >> comment? > 9125 spec is publicly accessible. Please provide a URL for the spec. >> A byte enable (BE) of 0x1111 suggests the CPU did a 32-bit I/O port >> read. Does the 9125 device only support one-byte I/O port accesses >> and when presented with larger request types it doesn't respond >> properly? > Yes, the hardware engineer had confirmed the situation. Please provide a URL for the erratum describing this 9125 issue. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
