On 02/01/2013 12:39 PM, Jason Gunthorpe wrote: > On Fri, Feb 01, 2013 at 10:57:20AM -0700, Stephen Warren wrote: ... >> I think the only difference on the Marvell HW is: >> >> * The overall total size of the physical address space is dynamic rather >> than fixed, because it's programmed through windows rather than >> hard-coded into HW. > > Is it hard coded on tegra? I thought there was a register set that was > used to set the overall PCI-E MMIO window location and size. I know > even on x86 the PCI window is set via register, though that typically > isn't disclosed except to bios writers.. There is a fixed (in HW) 1 GiB physical address window dedicated to PCIe. That window is divided between host controller registers, PCIe root port registers (since our root ports don't respond to configuration transactions), and regular PCIe accesses; config/MMIO/IO. There are registers in the host controller that configure the division of this space into config/MMIO/IO, so that can be dynamic. The DT bindings for the driver Thierry proposed hard-code those divisions in DT. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
