On Tue, Jan 29, 2013 at 04:45:07PM +0000, Arnd Bergmann wrote: > On Tuesday 29 January 2013, Thomas Petazzoni wrote: > > And the Linux PCI resource allocation code complies with this, so that > > if I have two PCI-to-PCI bridges (each having downstream a device with > > an I/O BAR), then the first PCI-to-PCI bridge gets its I/O base address > > register set to ADDR + 0x0, and the second bridge gets its I/O base > > address set to ADDR + 0x1000. And this doesn't play well with the > > requirements of Marvell address decoding windows for PCIe I/O regions, > > which must be 64 KB aligned. > > But we normally only assign a 64 KB I/O window to each PCI host bridge. > Requiring PCI bridges to be space 64 KB apart would mean that we cannot > actually support bridges at all. The PCI resource code uses full 32 bit integers when it handles IO addresses, so this actually does sort of work out. However, Thomas how did you recover the high bits of the IO window address from the bridge configuration? Are you reading the struct resource directly? That probably causes problems with hotplug/etc... If you look back in your old emails I outlined a solution to this using the MMU. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
