On Fri, Mar 07, 2025 at 03:06:31PM +0200, Ilpo Järvinen wrote: > On Tue, 4 Mar 2025, Bjorn Helgaas wrote: > > On Tue, Mar 04, 2025 at 03:51:08PM +0200, Ilpo Järvinen wrote: > > > Disallow Extended Tags and Max Read Request Size (MRRS) larger than > > > 128B for devices under Xeon 6 Root Ports if the Root Port is bifurcated > > > to x2. Also, 10-Bit Tag Requester should be disallowed for device > > > underneath these Root Ports but there is currently no 10-Bit Tag > > > support in the kernel. > > > > > > The normal path that writes MRRS is through > > > pcie_bus_configure_settings() -> pcie_bus_configure_set() -> > > > pcie_write_mrrs() and contains a few early returns that are based on > > > the value of pcie_bus_config. Overriding such checks with the host > > > bridge flag check on each level seems messy. Thus, simply ensure MRRS > > > is always written in pci_configure_device() if a device requiring the > > > quirk is detected. > > > > This is kind of weird. It's apparently not an erratum in the sense > > that something doesn't *work*, just something for "optimized PCIe > > performance"? > > > > What are we supposed to do with this? Add similar quirks for every > > random PCI controller? Scratching my head about what this means for > > the future. > > > > What bad things happen if we *don't* do this? Is this something we > > could/should rely on BIOS to configure for us? > > Even if BIOS configures this (I'm under impression they already do, I > had problem in finding a configuration in our lab on which this patch > had some effect). But my kernel was built with CONFIG_PCIE_BUS_DEFAULT, if > I set that to CONFIG_PCIE_BUS_PERFORMANCE, what BIOS did will be > overwritten. I despise those CONFIG_PCIE_BUS_* options, but have never managed to get rid of them. Unfortunate that something named "*_PERFORMANCE" will apparently result in *worse* performance in this respect.
