Re: [PATCH] PCI: Add PCI quirk to disable L0s ASPM state for RTL8125 2.5GbE Controller

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On 2025/3/6 06:20, Bjorn Helgaas wrote:
Sounds like this should be a documented erratum.  Realtek folks?  Or
maybe an erratum on the other end of the link, which looks like a CIX
Root Port:

   https://admin.pci-ids.ucw.cz/read/PC/1f6c/0001

Hi Bjorn,


Name: CIX P1 CD8180 PCI Express Root Port

0000:90:00.0 PCI bridge [0604]: Device [1f6c:0001]
0001:60:00.0 PCI bridge [0604]: Device [1f6c:0001]
0002:00:00.0 PCI bridge [0604]: Device [1f6c:0001]
0003:30:00.0 PCI bridge [0604]: Device [1f6c:0001]


This URL does not appear right, how should be changed, is it you? Or can you tell me who I should call to change it?

The correct answer is:
0000:90:00.0 PCI bridge [0604]: Device [1f6c:0001]
0001:C0:00.0 PCI bridge [0604]: Device [1f6c:0001]
0002:60:00.0 PCI bridge [0604]: Device [1f6c:0001]
0003:30:00.0 PCI bridge [0604]: Device [1f6c:0001]
0004:00:00.0 PCI bridge [0604]: Device [1f6c:0001]

The domain might be random, so whichever controller probes first, it's assigned first. The URL currently shows the BDF with one controller missing. That's the order in which we're going to controller probe.

Best regards,
Hans






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