From: LeoLiuoc <LeoLiu-oc@xxxxxxxxxxx> Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification r1.0, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: LeoLiuoc <LeoLiu-oc@xxxxxxxxxxx> --- include/uapi/linux/pci_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..0566c663beb7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -812,6 +812,10 @@ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ #define PCI_ERR_PREFIX_LOG 0x38 /* TLP Prefix LOG Register (up to 16 bytes) */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ -- 2.34.1
