Hi Lukas, On Tue, Feb 25, 2025 at 05:01:43AM +0100, Lukas Wunner wrote: > On Tue, Feb 25, 2025 at 11:06:50AM +0800, Feng Tang wrote: > > On Mon, Feb 24, 2025 at 07:12:11PM +0100, Lukas Wunner wrote: > > > On Mon, Feb 24, 2025 at 11:44:58AM +0800, Feng Tang wrote: > > > > @@ -255,8 +271,7 @@ static int get_port_device_capability(struct pci_dev *dev) > > > > * Disable hot-plug interrupts in case they have been enabled > > > > * by the BIOS and the hot-plug service driver is not loaded. > > > > */ > > > > - pcie_capability_clear_word(dev, PCI_EXP_SLTCTL, > > > > - PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE); > > > > + pcie_disable_hp_interrupts_early(dev); > > > > } > > > > > > Moving the Slot Control code from pciehp to portdrv (as is done in > > > patch 1 of this series) is hackish. It should be avoided if at all > > > possible. > > > > I tried to remove the code duplication of 2 waiting function, according > > to Bjorn's comment in https://lore.kernel.org/lkml/20250218223354.GA196886@bhelgaas/. > > Maybe I didn't git it right. Any suggestion? > > My point is just that you may not need to move the code from pciehp to > portdrv at all if you follow my suggestion. I see. > > > There might be some misunderstaning here :), I responded in > > https://lore.kernel.org/lkml/Z6LRAozZm1UfgjqT@U-2FWC9VHC-2323.local/ > > that your suggestion could solve our issue. > > Well, could you test it please? I don't have the hardware right now, will try to get from firmware developers. But from code logic, your suggestion can surely solve the issue unless I still miss something. From bug report (also commit log), the first PCIe hotplug command issued is here, and the second command comes from pciehp driver. In our kernel config, CONFIG_HOTPLUG_PCI_PCIE=y, so the first command won't happen, and all following commands come from pciehp driver, which setup its own waiting for command logic. > A small change like the one I proposed is definitely preferable to > moving dozens of lines of code around. Agree. > > > And the reason I didn't take it is I was afraid that it might hurt > > the problem what commit 2bd50dd800b5 ("PCI: PCIe: Disable PCIe port > > services during port initialization") tried to solve. > > > > As you mentioned, the comment for 2bd50dd800b5 is "a bit confusing", > > and I tried to guess in my previous reply: > > " > > I'm not sure what problem this piece of code try to avoid, maybe > > something simliar to the irq storm isseu as mentioned in the 2/2 patch? > > The code comments could be about the small time window between this > > point and the loading of pciehp driver, which will request_irq and > > enable hotplug interrupt again. > > " > > > > The code comment from 2bd50dd800b5 is: > > > > /* > > * Disable hot-plug interrupts in case they have been > > * enabled by the BIOS and the hot-plug service driver > > * is not loaded. > > */ > > > > The "is not loaded" has 2 possible meanings: > > 1. the pciehp driver is not loaded yet at this point inside > > get_port_device_capability(), and will be loaded later > > 2. the pciehp will never be loaded, i.e. CONFIG_HOTPLUG_PCI_PCIE=n > > > > If it's case 2, your suggestion can solve it nicely, but for case 1, > > we may have to keep the interrupt disabling. > > The pciehp driver cannot be bound to the PCIe port when > get_port_device_capability() is running. Because at that point, > portdrv is still figuring out which capabilities the port has and > it will subsequently instantiate the port service devices to which > the drivers (such as pciehp) will bind. Yes, the time window between here and the following initialization of pciehp service driver is very small, and your suggestion sounds quite safe to me. > So in that sense, case 1 cannot be what the code comment is > referring to. Hi Rafel, Could you help to confirm this? > > My point is that if CONFIG_HOTPLUG_PCI_PCIE=y, there may indeed be > another write to the Slot Control register before the command written > by portdrv has been completed. Because pciehp will write to the > register on probe. But in this case, there shouldn't be a need for > portdrv to quiesce the interrupt because pciehp will do that anyway > shortly afterwards. > > And in the CONFIG_HOTPLUG_PCI_PCIE=n case, pciehp will not quiesce > the interrupt, so portdrv has to do that. I believe that's what > the code comment is referring to. It should be safe to just write > to the Slot Control register without waiting for the command to > complete because there shouldn't be another Slot Control write > afterwards (not by pciehp anyway). > > If making the Slot Control write in portdrv conditional on > CONFIG_HOTPLUG_PCI_PCIE=n does unexpectedly *not* solve the issue, > please try to find out where the second Slot Control write is > coming from. E.g. you could amend pcie_capability_write_word() > with something like: > > if (pos == PCI_EXP_SLTCTL) { > pci_info(dev, "Writing %04hx SltCtl\n", val); > dump_stack(); > } Thanks for the suggestion, and we added similar debug to figure out them. Thanks, Feng
