On 22/2/25 10:34, Dan Williams wrote:
Bjorn Helgaas wrote:
On Thu, Dec 05, 2024 at 02:23:56PM -0800, Dan Williams wrote:
PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
enumerates new link capabilities and status added for Gen 6 devices. One
of the link details enumerated in that register block is the "Segment
Captured" status in the Device Status 3 register. That status is
relevant for enabling IDE (Integrity & Data Encryption) whereby
Selective IDE streams can be limited to a given requester id range
within a given segment.
s/requester id/Requester ID/ to match spec usage
Fixed.
+++ b/include/uapi/linux/pci_regs.h
@@ -749,6 +749,7 @@
#define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */
#define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */
+#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */
It doesn't look like lspci knows about this; is there something in
progress to add that?
https://git.kernel.org/pub/scm/utils/pciutils/pciutils.git/tree/lib/header.h?id=v3.13.0#n257
Alexey, do you have plans to follow up your IDE addition to pcituils
with this DEV3 support given the "Flit Mode" detection requirements of
"IDE RID Association Register 2"?
No sorry I do not, I do not have any device with this capability to try
lspci on. When/if I get one - then, sure. Do you have such device btw?
Thanks,
--
Alexey
