On Mon, Feb 24, 2025 at 01:01:17PM +0530, Thippeswamy Havalige wrote:
> Add support for AMD MDB (Multimedia DMA Bridge) IP core as Root Port.
>
> The Versal2 devices include MDB Module. The integrated block for MDB along
> with the integrated bridge can function as PCIe Root Port controller at
> Gen5 32-Gb/s operation per lane.
>
> Bridge supports error and legacy interrupts and are handled using platform
> specific interrupt line in Versal2.
s/legacy/INTx/ (I assume that's what you mean here)
> +config PCIE_AMD_MDB
> + bool "AMD MDB Versal2 PCIe Host controller"
> + depends on OF || COMPILE_TEST
> + depends on PCI && PCI_MSI
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want to enable PCIe controller support on AMD
> + Versal2 SoCs. The AMD MDB Versal2 PCIe controller is based on
> + DesignWare IP and therefore the driver re-uses the Designware core
> + functions to implement the driver.
s/Designware/DesignWare/
> +static void amd_mdb_intx_irq_unmask(struct irq_data *data)
> +{
> + struct amd_mdb_pcie *pcie = irq_data_get_irq_chip_data(data);
> + struct dw_pcie *pci = &pcie->pci;
> + struct dw_pcie_rp *port = &pci->pp;
> + unsigned long flags;
> + u32 val;
> +
> + raw_spin_lock_irqsave(&port->lock, flags);
> + val = FIELD_PREP(AMD_MDB_TLP_PCIE_INTX_MASK,
> + AMD_MDB_PCIE_INTR_INTX_ASSERT(data->hwirq));
> +
> + /*
> + * Writing '1' to a bit in AMD_MDB_TLP_IR_ENABLE_MISC enables that interrupt.
> + * Writing '0' has no effect.
Wrap to fit in 80 columns like the rest of the file.
> + */
> + pcie_write(pcie, val, AMD_MDB_TLP_IR_ENABLE_MISC);
> + raw_spin_unlock_irqrestore(&port->lock, flags);
> +}
