Hi Mani,
Thanks for reviewing & I ll update below comment in next patch.
Regards,
Thippeswamy H
-----Original Message-----
From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Sent: Monday, February 24, 2025 1:37 PM
To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx>
Cc: bhelgaas@xxxxxxxxxx; lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; Gogada, Bharat Kumar <bharat.kumar.gogada@xxxxxxx>
Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller
On Mon, Feb 24, 2025 at 01:11:43PM +0530, Thippeswamy Havalige wrote:
> The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> incorporate the Coherency and PCIe Gen5 Module, specifically the
> Next-Generation Compact Module (CPM5NC).
>
> The integrated CPM5NC block, along with the built-in bridge, can function
> as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> configuration.
>
> Bridge errors are managed using a specific interrupt line designed for
> CPM5N. INTx interrupt support is not available.
>
> Currently in this commit platform specific Bridge errors support is not
> added.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
One comment below which is not related to *this* patch, but should be fixed
separately (ideally before this patch).
> ---
> Changes in v2:
> - Update commit message.
> Changes in v3:
> - Address review comments.
> ---
> drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++-------
> 1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> index 81e8bfae53d0..a0815c5010d9 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
> CPM,
> CPM5,
> CPM5_HOST1,
> + CPM5NC_HOST,
> };
>
> /**
> @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
> {
> const struct xilinx_cpm_variant *variant = port->variant;
>
> + if (variant->version != CPM5NC_HOST)
> + return;
> +
> if (cpm_pcie_link_up(port))
> dev_info(port->dev, "PCIe Link is UP\n");
> else
> @@ -578,16 +582,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
>
> port->dev = dev;
>
> - err = xilinx_cpm_pcie_init_irq_domain(port);
> - if (err)
> - return err;
> + port->variant = of_device_get_match_data(dev);
> +
> + if (port->variant->version != CPM5NC_HOST) {
> + err = xilinx_cpm_pcie_init_irq_domain(port);
> + if (err)
> + return err;
> + }
>
> bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
> if (!bus)
> return -ENODEV;
Here, xilinx_cpm_free_irq_domains() should be called in the error path.
- Mani
--
மணிவண்ணன் சதாசிவம்
