On Mon, Feb 17, 2025 at 12:57:12PM +0530, Thippeswamy Havalige wrote: > The Xilinx Versal Net series has Coherency and PCIe Gen5 Module > Next-Generation compact (CPM5NC) block which supports Root Port > controller functionality at Gen5 speed. > > Error interrupts are handled CPM5NC specific interrupt line and > INTx interrupt is not support. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > Changes in v2: > - Update commit message to INTx > Changes in v3: > - None > --- > Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index b63a759ec2d7..d674a24c8ccc 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -18,6 +18,7 @@ properties: > - xlnx,versal-cpm-host-1.00 > - xlnx,versal-cpm5-host > - xlnx,versal-cpm5-host1 > + - xlnx,versal-cpm5nc-host > > reg: > items: > -- > 2.43.0 > -- மணிவண்ணன் சதாசிவம்
