Hi Sadhasivam,
> -----Original Message-----
> From: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> Sent: Friday, February 14, 2025 9:26 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@xxxxxxx>
> Cc: bhelgaas@xxxxxxxxxx; lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx;
> manivannan.sadhasivam@xxxxxxxxxx; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx;
> conor+dt@xxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>;
> Gogada, Bharat Kumar <bharat.kumar.gogada@xxxxxxx>
> Subject: Re: [PATCH v2 2/2] PCI: xilinx-cpm: Add support for Versal Net
> CPM5NC Root Port controller
>
> On Wed, Feb 12, 2025 at 11:20:59AM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
> > Next-Generation Compact Module (CPM5NC).
> >
> > The integrated CPM5NC block, along with the built-in bridge, can
> > function as a PCIe Root Port & supports the PCIe Gen5 protocol with
> > data transfer rates of up to 32 GT/s, capable of supporting up to a
> > x16 lane-width configuration.
> >
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. Intx interrupt support is not available.
> >
> > Currently in this patch Bridge errors support is not added.
>
> s/patch/commit,
Thank you for reviewing, Will update this in next patch.
>
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx>
> > ---
> > Changes in v2:
> > - Update commit message.
> > ---
> > drivers/pci/controller/pcie-xilinx-cpm.c | 85
> > ++++++++++++++----------
> > 1 file changed, 51 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index 81e8bfae53d0..c26ba662efd7 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
> > CPM,
> > CPM5,
> > CPM5_HOST1,
> > + CPM5NC_HOST,
> > };
> >
> > /**
> > @@ -483,31 +484,33 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
> > else
> > dev_info(port->dev, "PCIe Link is DOWN\n");
> >
> > - /* Disable all interrupts */
> > - pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
> > - XILINX_CPM_PCIE_REG_IMR);
> > -
> > - /* Clear pending interrupts */
> > - pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR) &
> > - XILINX_CPM_PCIE_IMR_ALL_MASK,
> > - XILINX_CPM_PCIE_REG_IDR);
> > -
> > - /*
> > - * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> > - * CPM SLCR block.
> > - */
> > - writel(variant->ir_misc_value,
> > - port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> > + if (variant->version != CPM5NC_HOST) {
>
> How about,
Thank you for reviewing, Will update this in next patch.
>
> if (variant->version != CPM5NC_HOST)
> return;
>
> Btw, what is the reason to skip these register settings for this controller?
> Especially the 'Bridge enable bit'.
Thank you for reviewing, Here Bridge enable bit is enabled with in IP & no need of Root Port
driver to handle Bridge enable bit.
>
> > + /* Disable all interrupts */
> > + pcie_write(port, ~XILINX_CPM_PCIE_IDR_ALL_MASK,
> > + XILINX_CPM_PCIE_REG_IMR);
> > +
> > + /* Clear pending interrupts */
> > + pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_IDR)
> &
> > + XILINX_CPM_PCIE_IMR_ALL_MASK,
> > + XILINX_CPM_PCIE_REG_IDR);
> > +
> > + /*
> > + * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> > + * CPM SLCR block.
>
> Please make use of 80 column width.
- Thank you for reviewing, Will update in next patch.
>
> > + */
> > + writel(variant->ir_misc_value,
> > + port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> > +
> > + if (variant->ir_enable) {
>
> nit: you don't need braces here.
Thank you for reviewing will update in next patch.
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
