On 2/11/2025 4:24 AM, Bjorn Helgaas wrote:
On Fri, Feb 07, 2025 at 04:58:59AM +0530, Krishna Chaitanya Chundru wrote:
The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register
gives us the offset from which ELBI starts. so use this offset and cfg
win to map these regions instead of doing the ioremap again.
+ /* Set the ECAM base */
+ writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
+ writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
+
+ /*
+ * The only device on root bus is the Root Port. Any access other than that
+ * should not go out of the link and should return all F's. Since the iATU
+ * is configured for the buses which starts after root bus, block the transactions
+ * starting from function 1 of the root bus to the end of the root bus (i.e from
+ * dbi_base + 4kb to dbi_base + 1MB) from going outside the link.
99% of this file fits in 80 columns. Wrap comments to do the same.
The text doesn't quite make sense because accesses to devices on the
root bus *never* involve a link. Only Root Ports have links and the
links all lead to buses other than the root bus.
Hi Bjorn,
As part of enumeration PCIe sw will look read the vendor id's and device
id's under PCIe bus0 to see if there is any multi root ports etc..like
bus0 device1, bus0 device2.
In the first 1MB only first 4kb is used as config space for root port,
remaining memory acts as PCIe memory i.e if we access this memory the
transactions will go outside the link which can trigger some unknown
error.
if there is read request for vendor id for bus0 device2 PCIe sw will
try to access after 4kb region which can cause unknown errors.
So we need to block these transaction from going through PCIe link.
I will update the comment description in the next patch.
- Krishna Chaitanya.
