On Thu, 13 Feb 2025 19:51:31 +0000, "Sven Peter" <sven@xxxxxxxxxxxxx> wrote: > > Hi, > > On Wed, Feb 12, 2025, at 10:55, Marc Zyngier wrote: > > On Tue, 11 Feb 2025 19:54:32 +0000, > > Alyssa Rosenzweig <alyssa@xxxxxxxxxxxxx> wrote: > >> > >> From: Hector Martin <marcan@xxxxxxxxx> > >> > >> This version of the hardware moved around a bunch of registers, so we > >> drop the old compatible for these and introduce register offset > >> structures to handle the differences. > >> > >> Signed-off-by: Hector Martin <marcan@xxxxxxxxx> > >> Signed-off-by: Alyssa Rosenzweig <alyssa@xxxxxxxxxxxxx> > >> --- > >> drivers/pci/controller/pcie-apple.c | 125 ++++++++++++++++++++++++++++++------ > >> 1 file changed, 105 insertions(+), 20 deletions(-) > >> > >> diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c > >> index 7f4839fb0a5b15a9ca87337f53c14a1ce08301fc..7c598334427cb56ca066890ac61143ae1d3ed744 100644 > ... > > > >> + else > >> + rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG); > >> + rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK); > >> + > > > > Can you elaborate on this particular change? > > > > I always assumed this was some clock-gating that needed to occur > > *before* the link training was started. This is now taking place after > > training, and the commit message doesn't say anything about it. > > It's been a while but as far as I can tell APPCLK seems to be related > to the IOMMUs attached to this controller. If it's disabled all reads > from the respective IOMMU MMIO either came back as 0xffff.. or SError > (don't remember which one it was) but pcie itself worked just fine > (until any device tried DMA ofc). > > At least on M1 this entire sequence only works because we already > setup PORT_APPCLK_EN inside m1n1. If we didn't do this (like e.g > for the thunderbolt pcie/dart) the DART probe would already fail. OK, so the exact location of this particular write doesn't matter as long as it happens before we start enabling a device on that port. I'm still perplexed by this one though: + if (pcie->hw->port_refclk) + rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK); + else + rmw_set(PHY_LANE_CFG_REFCLKCGEN, port->phy + PHY_LANE_CFG); which looks like it switches on the reference clock for the port. I have a very vague recollection that it was required early before m1n1/u-boot grew some PCI initialisation (yes, a long while ago). Thanks, M. -- Without deviation from the norm, progress is not possible.
