On Tue, Feb 11, 2025 at 01:24:40PM -0600, Terry Bowman wrote: > The CXL drivers use kernel trace functions for logging Endpoint and > Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality > is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL > Upstream Switch Ports. > > Introduce trace logging functions for both RAS correctable and > uncorrectable errors specific to CXL PCIe Ports. Additionally, update > the CXL Port Protocol Error handlers to invoke these new trace functions. > > Examples of the output from these changes is below. > > Correctable error: > cxl_port_aer_correctable_error: device=port1 parent=root0 status='Received Error From Physical Layer' > > Uncorrectable error: > cxl_port_aer_uncorrectable_error: device=port1 parent=root0 status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Erro' > > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> > Reviewed-by: Alejandro Lucero <alucerop@xxxxxxx> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx> Reviewed-by: Gregory Price <gourry@xxxxxxxxxx>
