On Mon, Feb 03, 2025 at 11:20:49PM +0530, manivannan.sadhasivam@xxxxxxxxxx wrote:
> On Sat, Feb 01, 2025 at 11:07:40AM -0600, Bjorn Helgaas wrote:
> > On Sat, Feb 01, 2025 at 09:54:16PM +0530, manivannan.sadhasivam@xxxxxxxxxx wrote:
> > > On Mon, Jan 27, 2025 at 06:41:50PM -0600, Bjorn Helgaas wrote:
> > > > On Thu, Jan 23, 2025 at 08:11:19AM +0000, Jianjun Wang (王建军) wrote:
> > > > > On Wed, 2025-01-15 at 23:01 +0530, Manivannan Sadhasivam wrote:
> > > > > > On Tue, Jan 07, 2025 at 01:20:58PM +0800, Jianjun Wang wrote:
> > > > > > > Remove the usage of virt_to_phys, as it will cause sparse warnings
> > > > > > > when
> > > > > > > building on some platforms.
> >
> > > > > > > snprintf(name, sizeof(name), "port%d", slot);
> > > > > > > - port->base = devm_platform_ioremap_resource_byname(pdev,
> > > > > > > name);
> > > > > > > + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > > > > > name);
> > > > > > > + if (!regs)
> > > > > > > + return -EINVAL;
> > > > > > > +
> > > > > > > + port->base = devm_ioremap_resource(dev, regs);
> > > > > > > if (IS_ERR(port->base)) {
> > > > > > > dev_err(dev, "failed to map port%d base\n", slot);
> > > > > > > return PTR_ERR(port->base);
> > > > > > > }
> > > > > > >
> > > > > > > + port->msg_addr = regs->start + PCIE_MSI_VECTOR;
> > > >
> > > > I think this still assumes that a CPU physical address
> > > > (regs->start) is the same as the PCI bus address used for MSI, so
> > > > this doesn't seem like the right solution to me.
Apart from the question of what type should be used, what do you think
about this part? I don't think we should assume that the address on
PCI is identical to the CPU physical address. IOMMUs and (I assume)
iATUs can make them different, can't they? If so, this looks like an
implicit assumption that PCI bus==CPU physical, and I think we should
make that a little more explicit somehow.
> > > > Apparently they happen to be the same on this platform because (I
> > > > assume) MSIs actually do work, but it's not a good pattern for
> > > > drivers to copy. I think what we really need is a dma_addr_t, and
> > > > I think there are one or two PCI controller drivers that do that.
> > >
> > > I don't see why we would need 'dma_addr_t' here. The MSI address is
> > > a static physical address on this platform and that is not a DMA
> > > address. Other drivers can *only* copy this pattern if they also
> > > have the physical address allocated for MSI.
> >
> > Isn't an MSI on PCI just a DMA write to a certain address?
>
> That's from the endpoint prespective when it triggers MSI.
>
> > My assumption is that if you put an analyzer on that link, an MSI
> > from a device would be structurally indistinguishable from a DMA
> > write from the device. The MSI uses a different address, but
> > doesn't it use the same size and kind of address, at least from
> > the PCIe protocol perspective?
>
> Yeah, but in this case the address allocated to MSI belongs to a
> hardcoded region in the host memory (not allocated by the DMA APIs
> which will have the region attributed as DMA capable). So it doesn't
> belong to the DMA domain, and we cannot use 'dma_addr_t'.
Doesn't .irq_compose_msi_msg() build the Message Address/Data pair
that is programmed into a device's MSI Capability or MSI-X Table?
The device will eventually use that to initiate a DMA write to that
address.
In that sense, I would argue that the Message Address does belong to
the DMA domain. I don't think the size of the address (32 vs 64 bits)
is determined by the CPU physical address size (phys_addr_t); it's
determined by the size of DMA addresses.
Bjorn
