Add support for getting the architecture for Cadence PCIe controllers
Store the architecture type in controller structure.
Signed-off-by: Manikandan K Pillai <mpillai@xxxxxxxxxxx>
---
.../controller/cadence/pcie-cadence-plat.c | 20 +++++++++++++++++++
drivers/pci/controller/cadence/pcie-cadence.h | 8 ++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index 0456845dabb9..d1cfb9847b7c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -37,6 +37,24 @@ static const struct cdns_pcie_ops cdns_plat_ops = {
.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
};
+static void cdns_pcie_ctlr_set_arch(struct cdns_pcie *pcie)
+{
+ /* Read register at offset 0xE4 of the config space
+ * The value for architecture is in the lower 4 bits
+ * Legacy-b'0010 and b'1111 for HPA-high performance architecture
+ */
+ u32 arch, reg;
+
+ reg = cdns_pcie_readl(pcie, CDNS_PCIE_CTRL_ARCH);
+ arch = FIELD_GET(CDNS_PCIE_CTRL_ARCH_MASK, reg);
+
+ if (arch == CDNS_PCIE_CTRL_HPA) {
+ pcie->is_hpa = true;
+ } else {
+ pcie->is_hpa = false;
+ }
+}
+
static int cdns_plat_pcie_probe(struct platform_device *pdev)
{
const struct cdns_plat_pcie_of_data *data;
@@ -74,6 +92,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
rc->pcie.ops = &cdns_plat_ops;
cdns_plat_pcie->pcie = &rc->pcie;
+ cdns_pcie_ctlr_set_arch(&rc->pcie);
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
if (ret) {
dev_err(dev, "failed to init phy\n");
@@ -101,6 +120,7 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
ep->pcie.ops = &cdns_plat_ops;
cdns_plat_pcie->pcie = &ep->pcie;
+ cdns_pcie_ctlr_set_arch(&ep->pcie);
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
if (ret) {
dev_err(dev, "failed to init phy\n");
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index f5eeff834ec1..2d9ecd923220 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -16,6 +16,13 @@
#define LINK_WAIT_USLEEP_MIN 90000
#define LINK_WAIT_USLEEP_MAX 100000
+/*
+ * Read completion time out reset value to decode controller architecture
+ */
+#define CDNS_PCIE_CTRL_ARCH 0xE4
+#define CDNS_PCIE_CTRL_ARCH_MASK GENMASK(3, 0)
+#define CDNS_PCIE_CTRL_HPA 0xF
+
/*
* Local Management Registers
*/
@@ -305,6 +312,7 @@ struct cdns_pcie {
struct resource *mem_res;
struct device *dev;
bool is_rc;
+ bool is_hpa;
int phy_count;
struct phy **phy;
struct device_link **link;
--
2.27.0
