On Thu, Jan 23, 2025 at 04:15:12PM +0800, Hans Zhang wrote:
> On 2025/1/23 15:40, Siddharth Vadapalli wrote:
> > On Thu, Jan 23, 2025 at 03:09:35PM +0800, Hans Zhang wrote:
> > > Add configuration space capability search API using struct cdns_pcie*
> > > pointer.
> > >
> > > Similar patches below have been merged.
> > > commit 5b0841fa653f ("PCI: dwc: Add extended configuration space capability
> > > search API")
> > > commit 7a6854f6874f ("PCI: dwc: Move config space capability search API")
> >
> > Similar patches being merged doesn't sound like a proper reason for
> > having a feature. Please provide details regarding why this is required.
> > Assuming that the intent for introducing this feature is to use it
> > later, it will be a good idea to post the patch for that as well in the
> > same series.
>
> For our SOC platform, the offset of some capability needs to be found during
> the initialization process, which I think should be put into the cadence
> public code
>
> eg:
>
> For API: cdns_pcie_find_capability
> Need to find PCI Express, then set link speed, retrain link, MaxPayload,
> MaxReadReq, Enable Relaxed Ordering.
>
> For API: cdns_pcie_find_ext_capability
> Need to find the Secondary PCIe Capability and set the GEN3 preset value.
> Find the Physical Layer 16.0 GT/s and set the GEN4 preset value.
>
> Development board based on our SOC, Radxa Orinon O6.
> https://radxa.com/products/orion/o6/
>
> Our controller driver currently has no plans for upstream and needs to wait
> for notification from the boss.
If/when you upstream code that needs this interface, include this
patch as part of the series. As Siddharth pointed out, we avoid
merging code that has no upstream users.
Bjorn
