On Wed, 2025-01-15 at 23:01 +0530, Manivannan Sadhasivam wrote:
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>
> On Tue, Jan 07, 2025 at 01:20:58PM +0800, Jianjun Wang wrote:
> > Remove the usage of virt_to_phys, as it will cause sparse warnings
> > when
> > building on some platforms.
> >
>
> Strange. What are those warnings and platforms?
There are some warning messages when building tests with different
configs on different platforms (e.g., allmodconfig.arm,
allmodconfig.i386, allmodconfig.mips, etc.):
pcie-mediatek.c:399:40: sparse: warning: incorrect type in argument 1
(different address spaces)
pcie-mediatek.c:399:40: sparse: expected void const volatile *x
pcie-mediatek.c:399:40: sparse: got void [noderef] __iomem *
pcie-mediatek.c:515:44: sparse: warning: incorrect type in argument 1
(different address spaces)
pcie-mediatek.c:515:44: sparse: expected void const volatile *x
pcie-mediatek.c:515:44: sparse: got void [noderef] __iomem *
Thanks.
>
> - Mani
>
> > Signed-off-by: Jianjun Wang <jianjun.wang@xxxxxxxxxxxx>
> > ---
> > drivers/pci/controller/pcie-mediatek.c | 19 ++++++++++++-------
> > 1 file changed, 12 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mediatek.c
> > b/drivers/pci/controller/pcie-mediatek.c
> > index 3bcfc4e58ba2..dc1e5fd6c7aa 100644
> > --- a/drivers/pci/controller/pcie-mediatek.c
> > +++ b/drivers/pci/controller/pcie-mediatek.c
> > @@ -178,6 +178,7 @@ struct mtk_pcie_soc {
> > * @phy: pointer to PHY control block
> > * @slot: port slot
> > * @irq: GIC irq
> > + * @msg_addr: MSI message address
> > * @irq_domain: legacy INTx IRQ domain
> > * @inner_domain: inner IRQ domain
> > * @msi_domain: MSI IRQ domain
> > @@ -198,6 +199,7 @@ struct mtk_pcie_port {
> > struct phy *phy;
> > u32 slot;
> > int irq;
> > + phys_addr_t msg_addr;
> > struct irq_domain *irq_domain;
> > struct irq_domain *inner_domain;
> > struct irq_domain *msi_domain;
> > @@ -393,12 +395,10 @@ static struct pci_ops mtk_pcie_ops_v2 = {
> > static void mtk_compose_msi_msg(struct irq_data *data, struct
> > msi_msg *msg)
> > {
> > struct mtk_pcie_port *port =
> > irq_data_get_irq_chip_data(data);
> > - phys_addr_t addr;
> >
> > /* MT2712/MT7622 only support 32-bit MSI addresses */
> > - addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > msg->address_hi = 0;
> > - msg->address_lo = lower_32_bits(addr);
> > + msg->address_lo = lower_32_bits(port->msg_addr);
> >
> > msg->data = data->hwirq;
> >
> > @@ -510,10 +510,8 @@ static int
> > mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
> > static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
> > {
> > u32 val;
> > - phys_addr_t msg_addr;
> >
> > - msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
> > - val = lower_32_bits(msg_addr);
> > + val = lower_32_bits(port->msg_addr);
> > writel(val, port->base + PCIE_IMSI_ADDR);
> >
> > val = readl(port->base + PCIE_INT_MASK);
> > @@ -913,6 +911,7 @@ static int mtk_pcie_parse_port(struct mtk_pcie
> > *pcie,
> > struct mtk_pcie_port *port;
> > struct device *dev = pcie->dev;
> > struct platform_device *pdev = to_platform_device(dev);
> > + struct resource *regs;
> > char name[10];
> > int err;
> >
> > @@ -921,12 +920,18 @@ static int mtk_pcie_parse_port(struct
> > mtk_pcie *pcie,
> > return -ENOMEM;
> >
> > snprintf(name, sizeof(name), "port%d", slot);
> > - port->base = devm_platform_ioremap_resource_byname(pdev,
> > name);
> > + regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > name);
> > + if (!regs)
> > + return -EINVAL;
> > +
> > + port->base = devm_ioremap_resource(dev, regs);
> > if (IS_ERR(port->base)) {
> > dev_err(dev, "failed to map port%d base\n", slot);
> > return PTR_ERR(port->base);
> > }
> >
> > + port->msg_addr = regs->start + PCIE_MSI_VECTOR;
> > +
> > snprintf(name, sizeof(name), "sys_ck%d", slot);
> > port->sys_ck = devm_clk_get(dev, name);
> > if (IS_ERR(port->sys_ck)) {
> > --
> > 2.46.0
> >
>
> --
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