On Tue, Jan 14, 2025 at 06:13:10PM -0600, Bjorn Helgaas wrote: > On Fri, Oct 11, 2024 at 03:00:41PM +0100, daire.mcnamara@xxxxxxxxxxxxx wrote: > > From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > > > > On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of > > three general-purpose Fabric Interface Controller (FIC) buses that > > encapsulate an AXI-M interface. That FIC is responsible for managing > > the translations of the upper 32-bits of the AXI-M address. On MPFS, > > the Root Port driver needs to take account of that outbound address > > translation done by the parent FIC bus before setting up its own > > outbound address translation tables. In all cases on MPFS, > > the remaining outbound address translation tables are 32-bit only. > > > > Limit the outbound address translation tables to 32-bit only. > > I don't quite understand what this is saying. It seems like the code > keeps only the low 32 bits of a PCI address and throws away any > address bits above the low 32. > > If that's what the FIC does, I wouldn't describe the FIC as > "translating the upper 32 bits" since it sounds like the translation > is just truncation. > > I guess it must be more complicated than that? I assume you can still > reach BARs that have PCI addresses above 4GB using CPU loads/stores? > > The apertures through the host bridge for MMIO access are described by > DT ranges properties, so this must be something that can't be > described that way? Ping? I'd really like to understand this before the v6.14 merge window opens on Sunday. Bjorn
