On Mon, Jan 6, 2025 at 3:33 AM Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> wrote: > > Some controllers and endpoints provide provision to program the entry > delays of L0s & L1 which will allow the link to enter L0s & L1 more > aggressively to save power. > > As per PCIe spec 6 sec 4.2.5.6, the number of Fast Training Sequence (FTS) > can be programmed by the controllers or endpoints that is used for bit and > Symbol lock when transitioning from L0s to L0 based upon the PCIe data rate > FTS value can vary. So define a array for each data rate for nfts. > > These values needs to be programmed before link training. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> > --- > - This change was suggested in this patch: https://lore.kernel.org/all/20241211060000.3vn3iumouggjcbva@thinkpad/ > --- > dtschema/schemas/pci/pci-bus-common.yaml | 16 ++++++++++++++++ Do these properties apply to any link like downstream ports on a PCIe switch? > 1 file changed, 16 insertions(+) > > diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml > index 94b648f..f0655ba 100644 > --- a/dtschema/schemas/pci/pci-bus-common.yaml > +++ b/dtschema/schemas/pci/pci-bus-common.yaml > @@ -128,6 +128,16 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [ 1, 2, 4, 8, 16, 32 ] > > + nfts: Kind of short. How about num-fts? Or is "NFTS" a PCI term? > + description: > + Number of Fast Training Sequence (FTS) used during L0s to L0 exit for bit > + and Symbol lock. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 5 Need to define what is each entry? Gen 1 to 5? > + items: > + maximum: 255 Why not use uint8 array then? > + > reset-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > @@ -150,6 +160,12 @@ properties: > description: Disables ASPM L0s capability > type: boolean > > + aspm-l0s-entry-delay-ns: > + description: Aspm l0s entry delay. > + > + aspm-l1-entry-delay-ns: > + description: Aspm l1 entry delay. > + > vpcie12v-supply: > description: 12v regulator phandle for the slot > > -- > 2.34.1 > >
