On Thu, Jan 02, 2025 at 05:00:16PM +0530, Varadarajan Narayanan wrote:
> From: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
>
> Add Qualcomm PCIe UNIPHY 28LP driver support present
> in Qualcomm IPQ5332 SoC and the phy init sequence.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
> Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx>
> ---
> v5: * Use 'num-lanes' to differentiate instead of '3x1' or '3x2'
> in compatible string
> * Drop compatible specific init data as there is only one
> compatible string
> * Fix header file order
>
> v4: Fix uppercase hex digit
> Use phy->id for pipe clock source
>
> v3: Added 'Reviewed-by: Dmitry Baryshkov' and made following updates
> s/unsigned int/u32/g
> Fix 'lane_offset' comments
> Fix #define tab -> space
> Fix mixed case hex numbers
> Fix licensing & owner
> Change for-loop pointer to use [] instead of ->
> Use 'less than max' instead of 'not equal to max' in termination condition
> Smatch and Coccinelle passed
>
> v2: Drop IPQ5018 related code and data
> Use uniform prefix for struct names
> Place "}, {", on the same line
> In qcom_uniphy_pcie_init(), use for-loop instead of while
> Swap reset and clock disable order in qcom_uniphy_pcie_power_off
> Add reset assert to qcom_uniphy_pcie_power_on's error path
> Use macros for usleep duration
> Inlined qcom_uniphy_pcie_get_resources & use devm_platform_get_and_ioremap_resource
> Drop 'clock-output-names' from phy_pipe_clk_register
> ---
> drivers/phy/qualcomm/Kconfig | 12 +
> drivers/phy/qualcomm/Makefile | 1 +
> .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 287 ++++++++++++++++++
> 3 files changed, 300 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
>
[...]
> +
> +static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
> +{
> + struct phy_provider *phy_provider;
> + struct device *dev = &pdev->dev;
> + struct qcom_uniphy_pcie *phy;
> + struct phy *generic_phy;
> + int ret;
> +
> + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
> + if (!phy)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, phy);
> + phy->dev = &pdev->dev;
> +
> + phy->data = of_device_get_match_data(dev);
> + if (!phy->data)
> + return -EINVAL;
> +
> + ret = of_property_read_u32(of_node_get(dev->of_node), "num-lanes",
Who will put the reference count which you have just got?
> + &phy->lanes);
> + if (ret)
> + phy->lanes = 1;
phy->lanes = 1;
of_property_read_u32(np, "num-lanes", &phy->lanes);
> +
> + ret = qcom_uniphy_pcie_get_resources(pdev, phy);
> + if (ret < 0)
> + return dev_err_probe(&pdev->dev, ret,
> + "failed to get resources: %d\n", ret);
> +
> + generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
> + if (IS_ERR(generic_phy))
> + return PTR_ERR(generic_phy);
> +
> + phy_set_drvdata(generic_phy, phy);
> +
> + ret = phy_pipe_clk_register(phy, generic_phy->id);
> + if (ret)
> + dev_err(&pdev->dev, "failed to register phy pipe clk\n");
> +
> + phy_provider = devm_of_phy_provider_register(phy->dev,
> + of_phy_simple_xlate);
> + if (IS_ERR(phy_provider))
> + return PTR_ERR(phy_provider);
> +
> + return 0;
> +}
> +
> +static struct platform_driver qcom_uniphy_pcie_driver = {
> + .probe = qcom_uniphy_pcie_probe,
> + .driver = {
> + .name = "qcom-uniphy-pcie",
> + .of_match_table = qcom_uniphy_pcie_id_table,
> + },
> +};
> +
> +module_platform_driver(qcom_uniphy_pcie_driver);
> +
> +MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
>
>
> --
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--
With best wishes
Dmitry
