"To disable a BAR (in any of the three schemes), your application can write â??0â?? to the LSB of the BAR mask register." dw_pcie_ep_reset_bar() calls __dw_pcie_ep_reset_bar(), which will write a zero to the LSB of the BAR mask register: https://github.com/torvalds/linux/blob/v6.13-rc3/drivers/pci/controller/dwc/pcie-designware-ep.c#L50 > > > https://github.com/torvalds/linux/blob/v6.13-rc3/drivers/pci/controller/dwc/pcie-designware-ep.c#L47-L52 > > And even if each endpoint driver marks "BAR_RESERVED" to the features, it is > only referred to as excluded BARs when searching for free BARs. So the host > will recognize this "reserved" BAR. A BAR that has been disabled on the EP side, will not have a size/ be visible on host side. Like I said, rk3588 calls dw_pcie_ep_reset_bar() on all BARs in EP init, like most DWC based EPC drivers, and marks BAR4 as reserved. This is how it looks on the host side during enumeration: [ 25.496645] pci 0000:01:00.0: [1d87:3588] type 00 class 0xff0000 PCIe Endpoint [ 25.497322] pci 0000:01:00.0: BAR 0 [mem 0x00000000-0x000fffff] [ 25.497863] pci 0000:01:00.0: BAR 1 [mem 0x00000000-0x000fffff] [ 25.498400] pci 0000:01:00.0: BAR 2 [mem 0x00000000-0x000fffff] [ 25.498937] pci 0000:01:00.0: BAR 3 [mem 0x00000000-0x000fffff] [ 25.499498] pci 0000:01:00.0: BAR 5 [mem 0x00000000-0x000fffff] [ 25.500036] pci 0000:01:00.0: ROM [mem 0x00000000-0x0000ffff pref] [ 25.500861] pci 0000:01:00.0: supports D1 D2 [ 25.501240] pci 0000:01:00.0: PME# supported from D0 D1 D3hot Likewise the looping in pci_endpoint_test.c will skip disabled BARs, e.g.: https://github.com/torvalds/linux/blob/v6.13-rc3/drivers/misc/pci_endpoint_test.c#L940-L943 Since test->bar[bar] will be NULL for BARs that are disabled. Kind regards, Niklas
