Here's my renewed proposal to fix the boot hang reported by Niklas
when enabling the bandwidth controller on Intel JHL7540 "Titan Ridge 2018"
Thunderbolt controllers.
@Niklas, could you re-test this?
I believe I've addressed all the feedback on v1, please let me know
if I've missed anything.
Changes v1 -> v2:
* [PATCH 2/3] PCI: Honor Max Link Speed when determining supported speeds
* Use PCI_EXP_LNKCAP2_SLS_2_5GB as lowest bit in GENMASK() macro
(Ilpo, Niklas).
* Mention user-visible issues addressed by the patch in commit message
(Bjorn).
* [PATCH 1/3] PCI: Assume 2.5 GT/s if Max Link Speed is undefined
* New patch to prevent invocation of malformed GENMASK(0, lowest) macro.
* [PATCH 3/3] PCI/bwctrl: Enable only if more than one speed is supported
* New patch to prevent the boot hang. This is a future-proof alternative
to Niklas' patch.
Link to v1, prior discussion and Niklas' patch:
https://lore.kernel.org/r/e3386d62a766be6d0ef7138a001dabfe563cdff8.1733991971.git.lukas@xxxxxxxxx/
https://lore.kernel.org/r/db8e457fcd155436449b035e8791a8241b0df400.camel@xxxxxxxxxx/
https://lore.kernel.org/r/20241207-fix_bwctrl_thunderbolt-v1-1-b711f572a705@xxxxxxxxxx/
https://lore.kernel.org/r/20241213-fix_bwctrl_thunderbolt-v2-1-b52fef641dfc@xxxxxxxxxx/
Lukas Wunner (3):
PCI: Assume 2.5 GT/s if Max Link Speed is undefined
PCI: Honor Max Link Speed when determining supported speeds
PCI/bwctrl: Enable only if more than one speed is supported
drivers/pci/pci.c | 13 +++++++++++--
drivers/pci/pcie/portdrv.c | 4 +++-
2 files changed, 14 insertions(+), 3 deletions(-)
--
2.43.0
