在 2024/12/11 10:53, Shawn Lin 写道:
Add support for Rockchip SoCs by adding vendor ID to the vendor list.
And fix the lane-event based enable/disable/read process which is slightly
different on Rockchip SoCs, by checking vendor ID.
Signed-off-by: Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
---
drivers/perf/dwc_pcie_pmu.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c
index 9cbea96..b3276b8 100644
--- a/drivers/perf/dwc_pcie_pmu.c
+++ b/drivers/perf/dwc_pcie_pmu.c
@@ -108,6 +108,7 @@ static const struct dwc_pcie_vendor_id dwc_pcie_vendor_ids[] = {
{.vendor_id = PCI_VENDOR_ID_ALIBABA },
{.vendor_id = PCI_VENDOR_ID_AMPERE },
{.vendor_id = PCI_VENDOR_ID_QCOM },
+ {.vendor_id = PCI_VENDOR_ID_ROCKCHIP },
Hi, Shawn,
Bjorn is working on fixing the VSEC matching[1], could you rebase on his lastest patch?
[1] https://lore.kernel.org/r/20231012162512.GA1069387@bhelgaas
Best Regards,
Shuai
{} /* terminator */
};
@@ -256,12 +257,27 @@ static const struct attribute_group *dwc_pcie_attr_groups[] = {
NULL
};
+static void dwc_pcie_pmu_lane_event_enable_for_rk(struct pci_dev *pdev,
+ u16 ras_des_offset,
+ bool enable)
+{
+ if (enable)
+ pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+ DWC_PCIE_CNT_ENABLE | DWC_PCIE_PER_EVENT_ON);
+ else
+ pci_clear_and_set_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+ DWC_PCIE_CNT_ENABLE, DWC_PCIE_PER_EVENT_ON);
+}
+
static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu,
bool enable)
{
struct pci_dev *pdev = pcie_pmu->pdev;
u16 ras_des_offset = pcie_pmu->ras_des_offset;
+ if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+ return dwc_pcie_pmu_lane_event_enable_for_rk(pdev, ras_des_offset, enable);
+
if (enable)
pci_clear_and_set_config_dword(pdev,
ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
@@ -287,9 +303,14 @@ static u64 dwc_pcie_pmu_read_lane_event_counter(struct perf_event *event)
{
struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu);
struct pci_dev *pdev = pcie_pmu->pdev;
+ int event_id = DWC_PCIE_EVENT_ID(event);
u16 ras_des_offset = pcie_pmu->ras_des_offset;
u32 val;
+ if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+ pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+ event_id << 16);
+
pci_read_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_DATA, &val);
return val;