On Mon, Dec 09, 2024 at 03:40:16PM +0000, Will Deacon wrote:
> On Fri, Dec 06, 2024 at 10:54:57AM -0600, Bjorn Helgaas wrote:
> > On Fri, Dec 08, 2023 at 10:56:51AM +0800, Shuai Xue wrote:
> > > This commit adds the PCIe Performance Monitoring Unit (PMU) driver support
> > > for T-Head Yitian SoC chip. Yitian is based on the Synopsys PCI Express
> > > Core controller IP which provides statistics feature. The PMU is a PCIe
> > > configuration space register block provided by each PCIe Root Port in a
> > > Vendor-Specific Extended Capability named RAS D.E.S (Debug, Error
> > > injection, and Statistics).
> >
> > > +#define DWC_PCIE_VSEC_RAS_DES_ID 0x02
> >
> > > +static const struct dwc_pcie_vendor_id dwc_pcie_vendor_ids[] = {
> > > + {.vendor_id = PCI_VENDOR_ID_ALIBABA },
> > > + {} /* terminator */
> > > +};
> >
> > > +static bool dwc_pcie_match_des_cap(struct pci_dev *pdev)
> > > +{
> > > + const struct dwc_pcie_vendor_id *vid;
> > > + u16 vsec;
> > > + u32 val;
> > > +
> > > + if (!pci_is_pcie(pdev) || !(pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT))
> > > + return false;
> > > +
> > > + for (vid = dwc_pcie_vendor_ids; vid->vendor_id; vid++) {
> > > + vsec = pci_find_vsec_capability(pdev, vid->vendor_id,
> > > + DWC_PCIE_VSEC_RAS_DES_ID);
> >
> > This looks wrong to me, and it promotes a misunderstanding of how VSEC
> > Capabilities work. The VSEC ID is defined by the vendor, so we have
> > to check both the Vendor ID and the VSEC ID before we know what this
> > VSEC Capability is.
>
> Thanks for pointing this out! The code's been merged for a while now,
> so we'll need to fix what we have rather than revert it, I think.
Yep, for sure.
> Any chance you could send a patch with those, please? I'm also not able
> to test this stuff, but I'm sure Ilkka would help us out.
Posted at https://lore.kernel.org/linux-pci/20241209222938.3219364-1-helgaas@xxxxxxxxxx
Bjorn
