On 12/3/24 23:25, Bjorn Helgaas wrote:
On Tue, Nov 26, 2024 at 04:51:15PM +0100, Christian Bruel wrote:
Document the bindings for STM32MP25 PCIe Controller configured in
root complex mode.
Supports 4 legacy interrupts and MSI interrupts from the ARM
GICv2m controller.
s/legacy/INTx/
STM32 PCIe may be in a power domain which is the case for the STM32MP25
based boards.
Supports wake# from wake-gpios
s/wake#/WAKE#/
+ wake-gpios:
+ description: GPIO controlled connection to WAKE# input signal
I'm not a hardware guy, but this sounds like a GPIO that *reads*
WAKE#, not controls it.
Rephrasing as
"GPIO used as WAKE# input signal" (output for the endpoint bindings)
+ pcie@48400000 {
+ compatible = "st,stm32mp25-pcie-rc";
+ device_type = "pci";
+ num-lanes = <1>;
num-lanes applies to a Root Port, not to a Root Complex. I know most
bindings conflate Root Ports with the Root Complex, maybe because many
of these controllers only support a single Root Port?
But are we ever going to separate these out? I assume someday
controllers will support multiple Root Ports and/or additional devices
on the root bus, like RCiEPs, RCECs, etc., and we'll need per-RP phys,
max-link-speed, num-lanes, reset-gpios, etc.
Seems like it would be to our benefit to split out the Root Ports when
we can, even if the current hardware only supports one, so we can
start untangling the code and data structures.
OK. and we support only 1 lane anyway, so drop it.
thanks,
Bjorn
