On 27.11.2024 2:42 AM, Krishna Chaitanya Chundru wrote: > > > On 11/16/2024 4:49 PM, Konrad Dybcio wrote: >> On 16.11.2024 2:37 AM, Krishna chaitanya chundru wrote: >>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >>> rates used in lane equalization procedure. >>> >>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx> >>> --- >>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index a36076e3c56b..6a2074297030 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>> phys = <&pcie6a_phy>; >>> phy-names = "pciephy"; >>> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; >> >> If we make all of these presets u8 arrays, we can use the: >> >> property = [0xff 0xff 0xff 0xff]; >> >> syntax >> >> Konrad > we can't make the property as u8 as each index represents single lane > and for 8 GT/s data rates each value needs 16bits. So for 8 GT/s we have > to use u16 array only. In patch 4 you write them one bit at at time anyway, you can split the u16 value into 2 bytes, which will save you on some ifs down the line. Konrad
