On Tue, Nov 26, 2024 at 11:22:51AM +0100, Neil Armstrong wrote:
> Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
> to the host CPUs. This interrupt can be used by the device driver to
> identify events such as PCIe link specific events, safety events, etc...
>
> Hence, add it to the PCIe RC node along with the existing MSI interrupts.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..f394fadf11f9ac1f781d31f514946bd5060fa56f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2233,7 +2233,8 @@ pcie0: pcie@1c00000 {
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "msi0",
> "msi1",
> "msi2",
> @@ -2241,7 +2242,8 @@ pcie0: pcie@1c00000 {
> "msi4",
> "msi5",
> "msi6",
> - "msi7";
> + "msi7",
> + "global";
>
> clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> @@ -2365,7 +2367,8 @@ pcie1: pcie@1c08000 {
> <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "msi0",
> "msi1",
> "msi2",
> @@ -2373,7 +2376,8 @@ pcie1: pcie@1c08000 {
> "msi4",
> "msi5",
> "msi6",
> - "msi7";
> + "msi7",
> + "global";
>
> clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
>
> --
> 2.34.1
>
--
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