Hi Lukas,
I added comments below.
On 11/14/2024 9:45 AM, Lukas Wunner wrote:
> On Wed, Nov 13, 2024 at 03:54:17PM -0600, Terry Bowman wrote:
>> --- a/drivers/pci/pci.c
>> +++ b/drivers/pci/pci.c
>> @@ -5038,6 +5038,20 @@ static u16 cxl_port_dvsec(struct pci_dev *dev)
>> PCI_DVSEC_CXL_PORT);
>> }
>>
>> +bool pcie_is_cxl_port(struct pci_dev *dev)
>> +{
>> + if (!pcie_is_cxl(dev))
>> + return false;
>> +
>> + if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
>> + (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
>> + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))
>> + return false;
>> +
>> + return cxl_port_dvsec(dev);
>> +}
>> +EXPORT_SYMBOL_GPL(pcie_is_cxl_port);
> This doesn't need to be exported because the only caller introduced
> in this series is in drivers/pci/pcie/aer.c (in patch 05/15), which
> is dependent on CONFIG_PCIEAER, which is bool not tristate.
Ok.
> The "!pcie_is_cxl(dev)" check at the top of the function is identical
> to the return value "cxl_port_dvsec(dev)". This looks redundant.
> However one cannot call pci_pcie_type() without first checking
> pci_is_pcie(). So I'm wondering if the "!pcie_is_cxl(dev)" check
> is actually erroneous and supposed to be "!pci_is_pcie(dev)"?
> That would make more sense to me.
I see pcie_is_cxl(dev) is different than cxl_port_dvsec(dev).They check different DVSECs.[1] CXL flexbus DVSEC presence is cached in pci_dev::is_cxl and returned by pcie_is_cxl().
This is used for indicating CXL device.
cxl_port_dvsec(dev) returns boolean based on presence of CXL port DVSEC to
indicate a CXL port device.
I don't believe they are redundant if you consider you can have a CXL device that
is not a CXL port device.
[1] - CXL 3.1, 8.1.1 Specification, PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment
> Alternatively, just return true instead of "cxl_port_dvsec(dev)".
> That would probably be the simplest solution here.
>
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -443,6 +443,7 @@ struct pci_dev {
>> unsigned int is_hotplug_bridge:1;
>> unsigned int shpc_managed:1; /* SHPC owned by shpchp */
>> unsigned int is_thunderbolt:1; /* Thunderbolt controller */
>> + unsigned int is_cxl:1; /* CXL alternate protocol */
> I suspect the audience consists mostly of CXL-unaware PCI developers,
> so spelling out Compute Express Link here (and omitting "alternate
> protocol" if it doesn't fit) might be more appropriate.
>
> Thanks,
>
> Lukas
Ok.
Regards,
Terry
