On Thu, Nov 07, 2024 at 06:24:25PM -0600, Bjorn Helgaas wrote: > On Thu, Nov 07, 2024 at 11:13:34AM +0000, Manivannan Sadhasivam wrote: > > On Thu, Nov 07, 2024 at 04:44:55PM +0800, Richard Zhu wrote: > > > Before sending PME_TURN_OFF, don't test the LTSSM stat. Since it's > > > safe to send PME_TURN_OFF message regardless of whether the link > > > is up or down. So, there would be no need to test the LTSSM stat > > > before sending PME_TURN_OFF message. > > > > What is the incentive to send PME_Turn_Off when link is not up? > > There's no need to send PME_Turn_Off when link is not up. > > But a link-up check is inherently racy because the link may go down > between the check and the PME_Turn_Off. Since it's impossible for > software to guarantee the link is up, the Root Port should be able to > tolerate attempts to send PME_Turn_Off when the link is down. > > So IMO there's no need to check whether the link is up, and checking > gives the misleading impression that "we know the link is up and > therefore sending PME_Turn_Off is safe." > I agree that the check is racy (not sure if there is a better way to avoid that), but if you send the PME_Turn_Off unconditionally, then it will result in L23 Ready timeout and users will see the error message. > > > Remove the L2 poll too, after the PME_TURN_OFF message is sent > > > out. Because the re-initialization would be done in > > > dw_pcie_resume_noirq(). > > > > As Krishna explained, host needs to wait until the endpoint acks the > > message (just to give it some time to do cleanups). Then only the > > host can initiate D3Cold. It matters when the device supports L2. > > The important thing here is to be clear about the *reason* to poll for > L2 and the *event* that must wait for L2. > > I don't have any DesignWare specs, but when dw_pcie_suspend_noirq() > waits for DW_PCIE_LTSSM_L2_IDLE, I think what we're doing is waiting > for the link to be in the L2/L3 Ready pseudo-state (PCIe r6.0, sec > 5.2, fig 5-1). > > L2 and L3 are states where main power to the downstream component is > off, i.e., the component is in D3cold (r6.0, sec 5.3.2), so there is > no link in those states. > > The PME_Turn_Off handshake is part of the process to put the > downstream component in D3cold. I think the reason for this handshake > is to allow an orderly shutdown of that component before main power is > removed. > > When the downstream component receives PME_Turn_Off, it will stop > scheduling new TLPs, but it may already have TLPs scheduled but not > yet sent. If power were removed immediately, they would be lost. My > understanding is that the link will not enter L2/L3 Ready until the > components on both ends have completed whatever needs to be done with > those TLPs. (This is based on the L2/L3 discussion in the Mindshare > PCIe book; I haven't found clear spec citations for all of it.) > > I think waiting for L2/L3 Ready is to keep us from turning off main > power when the components are still trying to dispose of those TLPs. > Not just disposing TLPs as per the spec, most endpoints also need to reset their state machine as well (if there is a way for the endpoint sw to delay sending L23 Ready). > So I think every controller that turns off main power needs to wait > for L2/L3 Ready. > > There's also a requirement that software wait at least 100 ns after > L2/L3 Ready before turning off refclock and main power (sec > 5.3.3.2.1). > Right. Usually, the delay after PERST# assert would make sure this, but in layerscape driver (user of dw_pcie_suspend_noirq) I don't see power/refclk removal. Richard Zhu/Frank, thoughts? - Mani -- மணிவண்ணன் சதாசிவம்
