On Fri, Nov 08, 2024 at 09:39:41AM +0100, lorenzo@xxxxxxxxxx wrote: > > On Thu, 2024-11-07 at 17:08 +0100, Lorenzo Bianconi wrote: > > > > On Thu, Nov 07, 2024 at 02:50:55PM +0100, Lorenzo Bianconi wrote: > > > > > In order to make the code more readable, move phy and mac > > > > > reset lines assert/de-assert configuration in .power_up > > > > > callback (mtk_pcie_en7581_power_up/mtk_pcie_power_up). > > > > > + /* > > > > > + * The controller may have been left out of reset by the > > > > > bootloader > > > > > + * so make sure that we get a clean start by asserting resets > > > > > here. > > > > > + */ > > > > > + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, > > > > > + pcie->phy_resets); > > > > > + reset_control_assert(pcie->mac_reset); > > > > > + usleep_range(10, 20); > > > > > > > > Unrelated to this patch, but since you're moving it, do you > > > > know what this delay is for? Can we add a #define and a spec > > > > citation for it? > > > > > > I am not sure about it, this was already there. @Jianjun Wang: > > > any input on it? > > > > This delay is used to ensure the reset is effective. A delay of > > 10us should be sufficient in this scenario. > > ack, so we can introduce a marco like: > > #define PCIE_RESET_TIME_US 10 > ... > > usleep_range(PCIE_RESET_TIME_US, 2 * PCIE_RESET_TIME_US); Unless this corresponds to a value specified by the PCIe base spec or CEM spec, this macro should be internal to pcie-mediatek-gen3.c.
