On Mon, Jul 22, 2024 at 02:15:13PM +0800, Richard Zhu wrote:
> The dw_pcie_suspend_noirq() function currently returns success directly
> if no endpoint (EP) device is connected. However, on some platforms, power
> loss occurs during suspend, causing dw_resume() to do nothing in this case.
> This results in a system halt because the DWC controller is not initialized
> after power-on during resume.
>
> Change call to deinit() in suspend and init() at resume regardless of
> whether there are EP device connections or not. It is not harmful to
> perform deinit() and init() again for the no power-off case, and it keeps
> the code simple and consistent in logic.
> ...
> - ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
> - PCIE_PME_TO_L2_TIMEOUT_US/10,
> - PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
> - if (ret) {
> - dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
> - return ret;
> + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
> + PCIE_PME_TO_L2_TIMEOUT_US/10,
> + PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
> + if (ret) {
> + dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
> + return ret;
> + }
Not related to this patch, but what's the reason for waiting for the
link to enter L2? There are a few other drivers that do this, but
most don't. Is there something else the driver needs to do after the
link is in L2?
> }
>
> if (pci->pp.ops->deinit)
> --
> 2.37.1
>
