On Thu, Oct 31, 2024 at 08:09:01PM -0700, Qiang Yu wrote:
> Currently, the cfg_1_9_0 which is being used for X1E80100 doesn't disable
> ASPM L0s. However, hardware team recommends to disable L0s as the PHY init
> sequence is not tuned support L0s. Hence reuse cfg_sc8280xp for X1E80100.
>
> Note that the config_sid() callback is not present in cfg_sc8280xp, don't
> concern about this because config_sid() callback is originally a no-op
> for X1E80100.
>
> Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
This one should also have been marked for backporting:
Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support")
Cc: stable@xxxxxxxxxxxxxxx # 6.9
Looks much better now either way:
Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
