Hello,
> > The PCI host controller on PolarFire SoC has multiple "instances", each
> > with their own bridge and ctrl address spaces. The original binding has
> > an "apb" register region, and it is expected to be set to the base
> > address of the host controllers register space. Defines in the driver
> > were used to compute the addresses of the bridge and ctrl address ranges
> > corresponding to instance1. Some customers want to use instance0 however
> > and that requires changing the defines in the driver, which is clearly
> > not a portable solution.
>
> The subject mentions "instance 1 or 2".
>
> This paragraph implies adding support for "instance0" ("customers want
> to use instance0").
>
> The DT patch suggests that we're adding support for "instance2"
> ("customers want to use instance2").
>
> Both patches suggest that the existing support is for "instance 1".
>
> Maybe what's being added is "instance 2", and this commit log should
> s/instance0/instance 2/ ? And probably s/instance1/instance 1/ so the
> style is consistent?
>
> Is this a "pick one or the other but not both" situation, or does this
> device support two independent PCIe controllers?
>
> I first thought this driver supported a single PCIe controller, and
> you were adding support for a second independent controller.
>
> But the fact that you say "the [singular] host controller on
> PolarFire", and you're not changing mc_host_probe() to call
> pci_host_common_probe() more than once makes me think there is only a
> single PCIe controller, and for some reason you can choose to operate
> it using either register set 1 or register set 2.
Conor, let me know if we need to clarify the commit log per Bjorn's
questions. If so, then I will do it directly on the branch.
Krzysztof
