On Fri, 25 Oct 2024 16:03:03 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:
> Introduce correctable and uncorrectable CXL PCIe port handlers.
>
> Use the PCIe port's device object to find the matching port or
> downstream port in the CXL topology. The matching port or downstream
> port will include the cached RAS register block.
>
> Invoke the existing __cxl_handle_ras() with the RAS registers as a
> parameter. __cxl_handle_ras() will log the RAS errors (if present)
> and clear the RAS status.
>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
> ---
> drivers/cxl/core/pci.c | 59 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index bb2fd7d04c4f..adb184d346ae 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -772,6 +772,65 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
> writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
> }
>
> +static int match_uport(struct device *dev, const void *data)
> +{
> + struct device *uport_dev = (struct device *)data;
> + struct cxl_port *port;
> +
> + if (!is_cxl_port(dev))
> + return 0;
> +
> + port = to_cxl_port(dev);
> +
> + return port->uport_dev == uport_dev;
> +}
> +
> +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev)
> +{
> + struct cxl_port *port __free(put_cxl_port) = NULL;
> + void __iomem *ras_base = NULL;
> +
> + if (!pdev)
> + return NULL;
> +
> + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) ||
> + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) {
> + struct cxl_dport *dport;
> +
> + port = find_cxl_port(&pdev->dev, &dport);
Scope of port is messy as the constructor and destructor
are not well associated. I'd drag a copy into each leg so they can
remain closer to each other.
Or don't use __free() as it's not adding much here.
> + ras_base = dport ? dport->regs.ras : NULL;
> + } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_UPSTREAM) {
> + struct device *port_dev;
> +
> + port_dev = bus_find_device(&cxl_bus_type, NULL, &pdev->dev,
> + match_uport);
> + if (!port_dev)
> + return NULL;
> +
> + port = to_cxl_port(port_dev);
> + ras_base = port ? port->uport_regs.ras : NULL;
> + }
> +
> + return ras_base;
> +}
> +
> +static void cxl_port_cor_error_detected(struct pci_dev *pdev)
> +{
> + void __iomem *ras_base = cxl_pci_port_ras(pdev);
> +
> + __cxl_handle_cor_ras(&pdev->dev, ras_base);
> +}
> +
> +static bool cxl_port_error_detected(struct pci_dev *pdev)
> +{
> + void __iomem *ras_base = cxl_pci_port_ras(pdev);
> + bool ue;
> +
> + ue = __cxl_handle_ras(&pdev->dev, ras_base);
> +
> + return ue;
> +}
> +
> void cxl_uport_init_ras_reporting(struct cxl_port *port)
> {
> /* uport may have more than 1 downstream EP. Check if already mapped. */
