On Fri, 25 Oct 2024 16:03:01 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:
> Add logic to map CXL PCIe upstream switch port (USP) RAS registers.
>
> Introduce 'struct cxl_regs' member into 'struct cxl_port' to store a
> pointer to the upstream port's mapped RAS registers.
>
> The upstream port may have multiple downstream endpoints. Before
> mapping AER registers check if the registers are already mapped.
>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
> ---
> drivers/cxl/core/pci.c | 17 +++++++++++++++++
> drivers/cxl/cxl.h | 4 ++++
> drivers/cxl/mem.c | 3 +++
> 3 files changed, 24 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 0bb61e39cf8f..53ca773557f3 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -773,6 +773,23 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
> writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
> }
>
> +void cxl_uport_init_ras_reporting(struct cxl_port *port)
> +{
> + /* uport may have more than 1 downstream EP. Check if already mapped. */
> + if (port->uport_regs.ras) {
> + dev_warn(&port->dev, "RAS is already mapped\n");
As before, warn seems inappropriate from the comment.
> + return;
> + }
> +
> + port->reg_map.host = &port->dev;
> + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs,
> + BIT(CXL_CM_CAP_CAP_ID_RAS))) {
> + dev_err(&port->dev, "Failed to map RAS capability.\n");
> + return;
> + }
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, CXL);
> +
