On Fri, 25 Oct 2024 16:02:54 -0500 Terry Bowman <terry.bowman@xxxxxxx> wrote: > CXL and AER drivers need the ability to identify CXL devices and CXL port > devices. > > First, add set_pcie_cxl() with logic checking for CXL Flexbus DVSEC > presence. The CXL Flexbus DVSEC presence is used because it is required > for all the CXL PCIe devices.[1] > > Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL > Flexbus presence. > > Add pcie_is_cxl() as a macro to return 'struct pci_dev::is_cxl', > > Add pcie_is_cxl_port() to check if a device is a CXL root port, CXL > upstream switch port, or CXL downstream switch port. Also, verify the > CXL extensions DVSEC for port is present.[1] > > [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended > Capability (DVSEC) ID Assignment, Table 8-2 > > Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx> Make sense to improve the trace point info if nothing else. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
