On Tue, Oct 22, 2024 at 07:26:31PM +0530, Manivannan Sadhasivam wrote: > On Tue, Oct 22, 2024 at 10:38:58AM +0200, Niklas Cassel wrote: > > On Tue, Oct 22, 2024 at 10:51:53AM +0900, Damien Le Moal wrote: > > > On 10/22/24 07:19, Bjorn Helgaas wrote: > > > > On Sat, Oct 12, 2024 at 08:32:40PM +0900, Damien Le Moal wrote: > > > However, if you think about a generic DMA controller, e.g. an ARM primecell > > pl330, I don't see how it that DMA controller will be able to perform > > transfers correctly if there is not an iATU mapping for the region that it > > is reading/writing to. > > > > I don't think the generic DMA controller can be used to read/write to remote > memory. It needs to be integrated with the PCIe IP so that it can issue PCIe > transactions. I'm not an expert, so I might of course be misunderstanding how things work. When the CPU performs an AXI read/write to a MMIO address within the PCIe controller (specifically the PCIe controller's outbound memory window), the PCIe controller translates that incoming read/write to a read/write on the PCIe bus. (The PCI address of the generated PCIe transaction will depend on how the iATU has been configured, which determines how reads/writes to the PCIe controller's outbound memory window should be translated to PCIe addresses.) If that is how it works when the CPU does the AXI read/write, why wouldn't things work the same if it is an generic DMA controller performing the AXI read/write to the MMIO address targeting the PCIe controller's outbound memory window? Kind regards, Niklas
