Hi Jonathan,
On 10/17/2024 8:50 AM, Jonathan Cameron wrote:
On Wed, 16 Oct 2024 13:16:34 -0500
Terry Bowman <Terry.Bowman@xxxxxxx> wrote:
Hi Jonathan,
On 10/16/24 12:14, Jonathan Cameron wrote:
On Tue, 8 Oct 2024 17:16:51 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:
RAS registers are not mapped for CXL root ports, CXL downstream switch
ports, or CXL upstream switch ports. To prepare for future RAS logging
and handling, the driver needs updating to map PCIe port RAS registers.
Give the upstream port is in next patch, I'd just mention that you
are adding mapping of RP and DSP here (This confused me before I noticed
the next patch).
Ok. Good point,
Refactor and rename cxl_setup_parent_dport() to be cxl_init_ep_ports_aer().
Update the function such that it will iterate an endpoint's dports to map
the RAS registers.
Rename cxl_dport_map_regs() to be cxl_dport_init_aer(). The new
function name is a more accurate description of the function's work.
This update should also include checking for previously mapped registers
within the topology, particularly with CXL switches. Endpoints under a
CXL switch may share a common downstream and upstream port, ensure that
the registers are only mapped once.
I don't understand why we need to do this for the ras registers but
it doesn't apply for HDM decoders for instance? Why can't
we map these registers in cxl_port_probe()?
We have seen downstream root ports with DVSECs that are not fully populated
immediately after booting. The plan here was to push out the RAS register
block mapping until as late as possible, in the memdev driver.
That needs debugging because simply pushing it later like this is
only going to make the race harder to hit unless we understand the
'why' of that. If there is a reason to delay, my gut feeling would
be to delay the cxl_port_probe() until things are stable rather
than just trying this a bit later.
This might be the whole link must train before CXL registers are
presented thing (a less than ideal corner of the CXL spec) but not
sure it would mean they weren't available in cxl_port_probe()
Jonathan
My understanding is there is no spec defined expectation for when CXL
config registers are ready.
We need Dan's feedback. He has asked several times for this to be located after
adding the endpoint in the memdev driver.
Regards,
Terry
