Hi Arnd,
On Wed, 02 Oct 2024 11:08:15 +0000
"Arnd Bergmann" <arnd@xxxxxxxx> wrote:
> On Mon, Sep 30, 2024, at 12:15, Herve Codina wrote:
>
> > + pci-ep-bus@0 {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + /*
> > + * map @0xe2000000 (32MB) to BAR0 (CPU)
> > + * map @0xe0000000 (16MB) to BAR1 (AMBA)
> > + */
> > + ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
> > + 0xe0000000 0x01 0x00 0x00 0x1000000>;
>
> I was wondering about how this fits into the PCI DT
> binding, is this a child of the PCI device, or does the
> "pci-ep-bus" refer to the PCI device itself?
This is a child of the PCI device.
The overlay is applied at the PCI device node and so, the pci-ep-bus is
a child of the PCI device node.
>
> Where do the "0x01 0x00 0x00" and "0x00 0x00 0x00" addresses
> come from? Shouldn't those be "02000010 0x00 0x00" and
> "02000014 0x00 0x00" to refer to the first and second
> relocatable 32-bit memory BAR?
These addresses are built dynamically by the PCI core during the PCI scan.
https://elixir.bootlin.com/linux/v6.11/source/drivers/pci/of_property.c#L101
They are use to reference the BARs.
0x00 for BAR0, 0x01 for BAR1, ...
The full DT, once PCI device are present, scanned and the overlay applied,
looks like the following:
--- 8< ---
pcie@d0070000 {
/* Node present on the base device tree */
compatible = "marvell,armada-3700-pcie";
#address-cells = <0x03>;
#size-cells = <0x02>;
ranges = <0x82000000 0x00 0xe8000000 0x00 0xe8000000 0x00 0x7f00000
0x81000000 0x00 0x00 0x00 0xefff0000 0x00 0x10000>;
device_type = "pci";
...
pci@0,0 {
/*
* Node created at runtime during the PCI scan
* This node is PCI bridge (class 604)
*/
#address-cells = <0x03>;
#size-cells = <0x02>;
device_type = "pci";
compatible = "pci11ab,100\0pciclass,060400\0pciclass,0604";
ranges = <0x82000000 0x00 0xe8000000 0x82000000 0x00 0xe8000000 0x00 0x4400000>;
...
dev@0,0 {
/*
* Node created at runtime during the
* PCI scan. This is my LAN966x PCI device.
*/
#address-cells = <0x03>;
interrupts = <0x01>;
#size-cells = <0x02>;
compatible = "pci1055,9660\0pciclass,020000\0pciclass,0200";
/*
* Ranges items allow to reference BAR0,
* BAR1, ... from children nodes.
* The property is created by the PCI core
* during the PCI bus scan.
*/
ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000
0x03 0x00 0x00 0x82010000 0x00 0xeb800000 0x00 0x800000
0x04 0x00 0x00 0x82010000 0x00 0xec000000 0x00 0x20000
0x05 0x00 0x00 0x82010000 0x00 0xec020000 0x00 0x2000>;
...
pci-ep-bus@0 {
/* Node added by the overlay */
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
/*
* Remap 0xe2000000 to BAR0 and
* 0xe0000000 to BAR1
*/
ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
0xe0000000 0x01 0x00 0x00 0x1000000>;
...
mdio@e200413c {
#address-cells = <0x01>;
resets = <0x25 0x00>;
#size-cells = <0x00>;
compatible = "microchip,lan966x-miim";
reg = <0xe200413c 0x24 0xe2010020 0x04>;
...
--- 8< ---
Hope this full picture helped to understand the address translations
involved.
Best regards,
Hervé
