The Xilinx Versal Premium series includes the CPM5 block, which supports
two Type-A Root Port controllers operating at Gen5 speed.
This patch adds a compatible string to distinguish between the two CPM5
Root Port controllers. The error interrupt registers and corresponding bits
for Controller 0 and Controller 1 are located at different offsets, making
it necessary to differentiate them.
By using the new compatible string, the driver can properly handle these
platform-specific differences between the controllers.
Signed-off-by: Thippeswamy Havalige <thippesw@xxxxxxx>
---
changes in v2:
--------------
Modify compatible string to differentiate controller 0 and controller 1
---
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index 989fb0fa2577..3783075661e2 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- xlnx,versal-cpm-host-1.00
- xlnx,versal-cpm5-host
+ - xlnx,versal-cpm5-host1-1
reg:
items:
--
2.34.1
