On Fri, Sep 13, 2024 at 09:24:29AM -0600, Keith Busch wrote: > On Fri, Sep 13, 2024 at 04:41:42PM +0530, Manivannan Sadhasivam wrote: > > I'm not able to understand the bug properly. The erratum indicates that the MSI > > from device reaches the VMD before other writes to the registers. So this is an > > ordering issue as MSI takes precedence over other writes from the device. > > > > So the workaround is to read the device register in the MSI handler to make sure > > the previous writes from the device are flushed. IIUC, once the MSI reaches the > > VMD, it will trigger the IRQ handler in the NVMe driver and in the handler, CQE > > status register is read first up. This flow matches with the workaround > > suggested. > > > > Is any write being performed to the NVMe device before reading any register in > > the MSI handler? Or the current CQE read is not able to satisfy the workaround? > > Please clarify. > > The CQE is not a device register. It exists in host memory, so reading > that from the driver isn't going to flush writes from IO devices. Ah okay, it makes sense now. Thanks for clarifying. For the workaround, does it make sense to have a platform specific quirk in the NVMe driver? Because, reading the NVMe device register from VMD driver doesn't look plausible to me. - Mani -- மணிவண்ணன் சதாசிவம்
