On Wed, Sep 11, 2024 at 08:56:28PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > From: Shashank Babu Chinta Venkata <quic_schintav@xxxxxxxxxxx> > > During high data transmission rates such as 16.0 GT/s, there is an > increased risk of signal loss due to poor channel quality and interference. > This can impact receiver's ability to capture signals accurately. Hence, > signal compensation is achieved through appropriate lane equalization > settings at both transmitter and receiver. This will result in increased > PCIe signal strength. > > While at it, let's also modify the pcie-tegra194 driver to make use of the > common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h. > > Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@xxxxxxxxxxx> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > [mani: dropped the code refactoring and minor changes] > Tested-by: Johan Hovold <johan+linaro@xxxxxxxxxx> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
