On Wed, Sep 04, 2024 at 02:48:30PM -0500, Wei Huang wrote: > On 9/4/24 13:49, Bjorn Helgaas wrote: > > On Thu, Aug 22, 2024 at 03:41:08PM -0500, Wei Huang wrote: > >> Hi All, > >> > >> TPH (TLP Processing Hints) is a PCIe feature that allows endpoint > >> devices to provide optimization hints for requests that target memory > >> space. These hints, in a format called steering tag (ST), are provided > >> in the requester's TLP headers and allow the system hardware, including > >> the Root Complex, to optimize the utilization of platform resources > >> for the requests. > >> > >> Upcoming AMD hardware implement a new Cache Injection feature that > >> leverages TPH. Cache Injection allows PCIe endpoints to inject I/O > >> Coherent DMA writes directly into an L2 within the CCX (core complex) > >> closest to the CPU core that will consume it. This technology is aimed > >> at applications requiring high performance and low latency, such as > >> networking and storage applications. > > > > Thanks for this example, it's a great intro. Suggest adding something > > similar to a patch commit log, since the cover letter is harder to > > find after this appears in git. > > I'll incorporate some of these descriptions into the TPH patches where > relevant. Additionally, I'll enhance the commit log for bnxt.c (patch > 11) with examples of the benefits. Sounds good. Another confusing point that would be helpful to mention is that TPH includes two pieces: Processing Hints and Steering Tags. As far as I can see, the only architected control of Processing Hints (bi-directional, requester, target, target w/ priority) is to enable/disable TPH or Extended TPH. But we *do* have significant software control over the Steering Tags.
