On 8/30/2024 1:53 PM, Krzysztof Kozlowski wrote:
On Fri, Aug 30, 2024 at 01:41:27PM +0530, Sricharan R wrote:
From: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5018.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Signed-off-by: Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
---
[v3] Added reviewed-by tags
.../phy/qcom,ipq5018-uniphy-pcie.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
new file mode 100644
index 000000000000..c04dd179eb8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5018-uniphy-pcie.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,ipq5018-uniphy-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm UNIPHY PCIe 28LP PHY controller for genx1, genx2
+
+maintainers:
+ - Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
+ - Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq5018-uniphy-pcie-gen2x1
+ - qcom,ipq5018-uniphy-pcie-gen2x2
... and now I wonder why there are two compatibles. Isn't the phy the
same? We talk about the same hardware?
We have 2 different physical phys. One with single lane and another
with dual lane. Its same IP, but for 2 lanes, 2 sets of the phy
specific registers needs to configured. So differentiating that here.
Regards,
Sricharan
