On 9/3/2024 13:25, Bjorn Helgaas wrote:
On Tue, Sep 03, 2024 at 12:31:00PM -0500, Mario Limonciello wrote:
On 9/3/2024 12:11, Bjorn Helgaas wrote:
...
8) The USB4 stack sees the device and assumes it is in D0, but it
seems to still be in D3cold. What is this based on? Is there a
config read that returns ~0 data when it shouldn't?
Yes there is. From earlier in the thread I have a [log] I shared.
The message emitted is from ring_interrupt_active():
"thunderbolt 0000:e5:00.5: interrupt for TX ring 0 is already enabled"
Right, that's in the cover letter, but I can't tell from this what the
ioread32(ring->nhi->iobase + reg) returned. It looks like this is an
MMIO read of BAR 0, not a config read.
Yeah. I suppose another way to approach this problem is to make
something else in the call chain poll PCI_PM_CTRL.
Polling at the start of nhi_runtime_resume() should also work. For the
"normal" scenario it would just be a single read to PCI_PM_CTRL.
Mika, thoughts?
