On Thu, Jun 14, 2012 at 6:55 AM, Tom Carr <tkcarr03873@xxxxxxxxx> wrote:
> Yinghai Lu <yinghai <at> kernel.org> writes:
>
>>
>> On Mon, Jun 11, 2012 at 12:32 PM, Tom Carr <tkcarr03873 <at> gmail.com> wrote:
>> >
>> > Yinghai, sorry about the direct email on Friday, I tried to reply back to
>> > the
>> > newsgroup but the send kept failing. Your suggestion worked but only if
>> > there
>> > were no drivers attached to the endpoints. If I load the driver for the
>> > endpoint
>> > at bus 6.0 and 9.0, then load the empty FPGA at bus 8.0, which is off of
>> > 4.8,
>> > and write 1 to /sys/bus/pci/remove the system crashes. Is there a
>> > requirement that all down stream devices be removed? I could not find any
>> > such
>> > requirement in any documentation. Here is the most of the stack trace.
>>
>> can you please try current linus kernel like
>> 3.4 or 3.5-rc1 ?
>>
>> looks like there is some stop/remove pci device code bug in old kernel.
>>
>> Thanks
>>
>> Yinghai
>>
>
> Yinghai, thank you for the help. Moving to 3.4 fixed the problem. I am now able
> to load the FPGA and bring the FPGA endpoint online using remove and rescan. I
> was curious if it would be possible to instruct the root complex port to
> allocate enough memory to deal with endpoints that come on line
> after the system is booted. With the solution I have now, the drivers for all
> the endpoints in the PCIe tree starting at the root port 1.2 have to be removed
> which means if they have to stop processing while the rescan is done. Since
> this is an embedded design, the endpoints and the memory they will use does
> not change. If the root could be instructed to allocate enough memory to deal
> with endpoints coming in later then only the switch port connected to the
> endpoint would need to be removed and the other endpoints should be able to
> continue to function. If you think this is doable and of value to others, I
> would be willing to make the change and offer it up for consideration.
that should be there already, but user need to specify the exact BDF ...
pci=option[,option...] [PCI] various PCI subsystem options:
resource_alignment=
Format:
[<order of
align>@][<domain>:]<bus>:<slot>.<func>[; ...]
Specifies alignment and device to reassign
aligned memory resources.
If <order of align> is not specified,
PAGE_SIZE is used as alignment.
PCI-PCI bridge can be specified, if resource
windows need to be expanded.
for bridge alignment will be the size.
Also your motherboard BIOS have problem, BIOS should treat 00:01.2 as
hotplug bridge.
Thanks
Yinghai
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