On Thu, Aug 15, 2024 at 06:57:23PM -0400, Jim Quinlan wrote: > Provide support for new chips with multiple inbound windows while > keeping the legacy support for the older chips. > > In existing chips there are three inbound windows with fixed purposes: the > first was for mapping SoC internal registers, the second was for memory, > and the third was for memory but with the endian swapped. Typically, only > one window was used. > > Complicating the inbound window usage was the fact that the PCIe HW would > do a baroque internal mapping of system memory, and concatenate the regions > of multiple memory controllers. > > Newer chips such as the 7712 and Cable Modem SOCs take a step forward and > drop the internal mapping while providing for multiple inbound windows. > This works in concert with the dma-ranges property, where each provided > range becomes an inbound window. Krzysztof, can you touch this up on your branch to s/SOCs/SoCs/ to match other usage above, and ... > + * The HW registers (and PCIe) use order-1 numbering for BARs. As > + * such, we have inbound_wins[0] unused and BAR1 starts at inbound_wins[1]. Rewrap this to fit in 80 columns like (most of) the rest of the file instead of 83? I don't think we gain anything by being wider here.
